SN74ALVCH16721 |
RFQ for SN74ALVCH16721 Required Field |
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| Technical/Catalog Information | SN74ALVCH16721DGGR |
| Vendor | Texas Instruments (VA) |
| Category | Integrated Circuits (ICs) |
| Mounting Type | Surface Mount |
| Package / Case | 56-TSSOP |
| Function | Standard |
| Number of Bits per Element | 20 |
| Number of Elements | 1 - Single |
| Current - Output High, Low | 24mA, 24mA |
| Output Type | Tri-State Non Inverted |
| Trigger Type | Positive Edge |
| Type | D-Type Bus |
| Packaging | Cut Tape (CT) |
| Operating Temperature | -40°C ~ 85°C |
| Delay Time - Propagation | 1ns |
| Frequency - Clock | 150MHz |
| Voltage - Supply | 1.65 V ~ 3.6 V |
| Drawing Number | 296; 4040078; DGG; 48, 56, 64 |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | SN74ALVCH16721DGGR SN74ALVCH16721DGGR 296 1147 1 ND 29611471ND 296-1147-1 |
| Product | Manufacturers | Pack | D/C |
| SN74ALVCH16721 | - | - | 07/08+ |
This 20-bit flip-flop is designed specifically for 1.65-V to 3.6-V VCC operation.
The 20 flip-flops of the SN74ALVCH16721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN) input is low. If CLKEN is high, no data is stored.
A buffered output-enable (OE) input places the 20 outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16721 is characterized for operation from 40°C to 85°C.
Features |
| · Member of the Texas Instruments WidebusTM Family· EPICTM (Enhanced-Performance Implanted CMOS) Submicron Process· ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)· Latch-Up Performance Exceeds 250 mA Per JESD 17· Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors· Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages |
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±50 mA
Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, JA (see Note 3): DGG package . . . . . . .. . . . . . . . . . . . .. 81°C/W
DGV package . . . . . . . . . . . . . . . . . . . . 86°C/W
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